LLM inference on Intel GPU; DNA for 3D nanostructures; regulating supply voltage and clock frequency; nanoscale PCM; GPGPU simulator; RISC-V MCU for ultra-low-power edge; heterogeneous integration of memristors; field-free spin-orbit torque devices.
New technical papers added to Semiconductor Engineering’s library this week.
|Efficient LLM inference solution on Intel GPU
|Three-dimensional nanoscale metal, metal oxide, and semiconductor frameworks through DNA-programmable assembly and templating
|Brookhaven National Laboratory, Columbia University, and Stony Brook University
|Dynamic Voltage and Frequency Scaling for Intermittent Computing
|Politecnico di Milano, Georgia Institute of Technology, Lahore University of Management Sciences, and Uppsala University
|Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory
|Stanford University, TSMC, NIST, University of Maryland, Theiss Research and Tianjin University
|Analyzing and Improving Hardware Modeling of Accel-Sim
|Universitat Politècnica de Catalunya
|X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge
|Heterogeneous Integration of Graphene and HfO2 Memristors
|Forschungszentrum Jülich, Jožef Stefan Institute, and JARA-FIT
|Perspectives on field-free spin-orbit torque devices for memory and computing applications
Technical Paper Library home
Liz Allan is an associate editor at Semiconductor Engineering.
Wanda Parisien is a computing expert who navigates the vast landscape of hardware and software. With a focus on computer technology, software development, and industry trends, Wanda delivers informative content, tutorials, and analyses to keep readers updated on the latest in the world of computing.