May 09, 2024

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In this, the third and final installment of this series, I will walk you through a real-world example to realize the benefits of analog-to-digital converter (ADC) decimation.

For the example below, I will use the Texas Instruments ADC32RF55, a dual-channel, 14-bit, 3GSPS radio-frequency sampling ADC with an integrated 48-bit coherent numerically controlled oscillator (NCO). This device supports a multiband output, allowing for the simultaneous capture of up to eight distinct RF bands using a single data converter. This data converter uses a Joint Electron Device Engineering Council JESD204B interface to transmit high-speed digital data to a field programmable gate array (FPGA).

*This is the third part of a series on ADC Decimation. Click here for part one.*

*Click here for part two.*

## Overcoming traditional limitations

In the traditional receiver signal chain discussed in part 2, a data converter used in conjunction with an upstream down-mixing stage captures high-frequency signals. A major drawback of this traditional approach is the inability to quickly change a system’s input band region without additional hardware. Historically, a dynamic system requires an adjustable synthesizer in place of the local oscillator, additional band-specific matching networks, active programmable gain and attenuation stages, filtering stages and many high-performance programmable switches.

The integration of a digital down converter (DDC) into the ADC directly removes a handful of these components, such as the adjustable synthesizer, band-specific matching circuits and programmable switches. With these RF-focused ADCs, you can now design a matching network to cover all frequencies of interest and use the data converter’s NCO for a modular down-mixing approach without these additional components. Furthermore, implementing decimation on the data converter improves the data throughput such that data is processed more efficiently downstream by the FPGA.

## Real-world example: High-bandwidth cluster analysis

Consider a system that uses a cluster of three 10MHz bandwidth signals at a carrier frequency of 900MHz and a cluster of seven 3MHz signals at a carrier frequency of 1,200MHz. Figure 1 is a fast Fourier transform (FFT) of the captured data in bypass mode showing the full-frequency spectrum containing these two clusters of wideband tones.

Without any upstream mixing stages, only a broadband spectrum is achievable using a high-speed data converter, assuming sufficient analog input bandwidth. As shown in Figure 1, the converter’s utilization is quite low, provided that only 150MHz worth of data is of interest across the entire 1,300MHz spectrum, a usage of approximately 11.5%. Therefore, 88.5% worth of data is additional overhead, containing nonuseful information, yet processing this data is mandatory.

Instead of operating in this wide-bandwidth mode, implementing decimation by 32 significantly reduces the bandwidth and additional processing overhead. Additionally, using the dual-band output mode enables the capture of both unique frequency bands using just a single channel of the ADC32RF55. Setting the NCO frequency for DDC1 to 900MHz captures the cluster of three 10MHz tones, as shown in Figure 2.

As a result of this decimation, the output data rate reduces by a factor of 32 and the lane rate drops from the 13Gbps rate in bypass mode to near 400Mbps. For the ADC32RF55, the minimum serializer deserializer (SerDes) rate is 500Mbps for the JESD204B interface, meaning that the decimation by 32 mode is actually too effective if all eight SerDes lanes are used. To avoid this issue, the device simply must operate with a reduced number of SerDes lanes, where each individual lane operates at a faster data rate.

Typically, there are many options when choosing the best configuration for your application based on the intended number of data lanes, as well as each lane’s data rate. In this example, implementing a four-lane dual-band configuration reduced the data rate to 1,600Mbps; that’s well within the ADC32RF55 JESD204B interface’s supported frequency range. Implementation of this mode has reduced the data overhead by a factor of 32 per output band. The NCO frequency of DDC2 is set to 1,200MHz and the ADC32RF55 captures the second cluster of tones, as shown in Figure 3.

Not only are these tones significantly easier to distinguish in the FFT visually, the decimation factor, M, directly improves the resolution bandwidth, and the resulting data inherently becomes more valuable.

Another notable benefit is the processing gain realized as a result of decimation. In the bypass spectrum shown in Figure 1, the noise floor of the captured spectrum is approximately –108dBFS, indicated by the red dashed line.

Using the derived processing gain equation from part 2 of this series, Equation 1 calculates the expected processing gain as approximately 16dB when decimating by a factor of 32:

This 16dB of processing gain effectively pushes the noise floor from –108dBFS to –124dBFS. The noise floor (indicated by the dashed red line) in both Figure 2 and Figure 3 confirm the processing gain, as the noise floor decreases from –108dBFS to –124dBFS. In many cases, the realized processing gain will fall short as a result of noise landing in the transition band of the DDC filter.

A proper FFT spectrum must incorporate a scaling factor, as shown in Equation 2, based on the number of samples, n, for each FFT computation:

The number of samples remained untouched throughout this example to show the improvement in the frequency domain directly as a result of the processing gain. In practical applications, if a higher resolution bandwidth is crucial, you could maintain the existing number of samples used in the FFT computation to directly leverage the processing gain. However, if the resolution bandwidth is not a priority, you could opt to reduce the number of samples used in the FFT computation. This adjustment, while balancing the benefits of the processing gain, would result in similar performance but with quicker computation times.

## Conclusion

As RF data converters exceed 10GSPS sampling rates and embrace higher resolutions, decimation offers numerous advantages. This innovation eliminates the need for expensive FPGAs capable of handling high serial data rates, enabling FPGA designers to save on input/output pins or high-speed transceiver lanes for the converter interface. Decimation not only enhances system design flexibility through effective frequency planning but also reduces downstream data processing requirements by minimizing data volume and facilitating the implementation of multiband outputs. The scalability of current converter technology to new integration levels enables the ADC to take on functions traditionally attributed to digital signal processors or FPGAs. This shift to digital simplifies the burden on the signal chain’s large digital engine by incorporating more digital features into modern ADCs.

Wanda Parisien is a computing expert who navigates the vast landscape of hardware and software. With a focus on computer technology, software development, and industry trends, Wanda delivers informative content, tutorials, and analyses to keep readers updated on the latest in the world of computing.