April 17, 2024
2:00 PM ET / 1:00 PM CT / 11:00 AM PT / 7:00 PM GMT
Duration: 1 hour
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Summary
As VPX systems enter the domain of PCI Express Gen4 and 100-Gigabit Ethernet, maintaining end-to-end signal integrity is changing from an important design element to a critical one. These data rates are at the very limit of what VPX can support, and they are impossible to achieve without careful analysis, simulation, design practices, and verification approaches.
Recognizing this, VITA started the VITA 68.3 Signal Integrity for Gen4+ Speeds working group to analyze the problem and draft standardized approaches to address these problems. Parallel to this, vendors have taken on the development of products using these high-performance interfaces, often having to invent their own methodologies for ensuring signal integrity.
In this webcast, we will look at the current state of VITA 68.3, as well as some real-world design use cases involving high-speed switches from Interface Concept and backplanes from Elma, and the lessons learned by both teams. HPEC performance will be discussed with reference to the cooling techniques considered that include 48.2 Conduction and 48.8 AFT, that allow the switches to operate at full performance under wide temperature and full bandwidth use cases.
Wanda Parisien is a computing expert who navigates the vast landscape of hardware and software. With a focus on computer technology, software development, and industry trends, Wanda delivers informative content, tutorials, and analyses to keep readers updated on the latest in the world of computing.
